Semiconductor memory device having plug contacted to a capacitor electrode and method for fabricating a capacitor of the semiconductor memory device

ABSTRACT

The present invention provides a semiconductor memory device and a method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier. The plug to be contacted to an electrode of a capacitor, comprises a diffusion barrier layer and a conducting layer. The conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized. Accordingly, it is possible to prevent the dielectric layer being contacted with the diffusion barrier, there by the leakage current may be reduced, and the capacitance of the capacitor may be increased.

FIELD OF THE INVENTION

[0001] The present invention relates to a method for fabricating asemiconductor memory device; and more particularly, to a method forfabricating a capacitor of semiconductor memory device.

DESCRIPTION OF THE PRIOR ART

[0002] A DRAM (Dynamic Random Access Memory) cell is a semiconductormemory device typically comprising one transistor and one capacitor, inwhich one bit of data is stored in a cell by using an electric charge. Acapacitor comprises of a lower electrode, a dielectric layer, and anupper electrode. One electrode of the capacitor is connected to thesource/drain junction of the transistor. Another electrode of thecapacitor is connected to a reference voltage line.

[0003] Advances in computer applications have increased the demand forhigher capacity memory chips. Decreasing the size of the memory cellsallows more memory cells to be packed into an integrated circuit.

[0004] The capacitance of a capacitor is proportional to the surfacearea of the electrodes and a dielectric constant of a dielectric layer.As the area of the memory cell has decreased, the capacitance of thecapacitors tends to decrease also, lowering the performance of thememory cells.

[0005] In order to increase the density of memory cells, stackedcapacitors have been proposed. Stacked capacitors are formed bypartially stacking the storage electrode over the transistor and overthe bit/word line, thereby effectively reducing the area used for eachmemory cell.

[0006] A plug is used to connect the lower electrode of the capacitorwith the source/drain junction of the transistor.

[0007] A method for fabricating a capacitor of a semiconductor memorydevice according to the conventional method is described referring toFIG. 1A to FIG. 1C.

[0008] As shown in FIG. 1A, an insulating layer 15 is formed over asemiconductor substrate 10, an isolation layer 11, such as field oxidelayer, and a transistor comprising a gate insulating layer 12, a gateelectrode 13 and the source/drain junctions 14. Thereafter, a plug 16 isformed in the interlayer insulating layer. The plug 16 is composed of aploysilicon layer 16A, an ohmic contact layer 16B and a diffusionbarrier layer 16C formed in a contact hole, exposing one of thesource/drain junctions 14.

[0009] As shown in FIG. 1B, a lower electrode 17 is formed on thediffusion barrier layer 16C by depositing and patterning a firstconductive layer. The diffusion barrier layer 16C may be exposed duringthe formation of the lower electrode 17 because of a mask misalignment.The mask misalignment is frequently occurred in a manufacturing processof a highly integrated device.

[0010] As shown in FIG. 1C, a dielectric layer 18 is formed on the lowerelectrode 17 and an upper electrode 19 is formed on the dielectric layer18. The dielectric layer 18 is formed with a material exhibiting a veryhigh dielectric constant, such as Barium strontium titanate (BaSrTiO₃,hereafter abbreviated BST), to increase the capacitance in a highlyintegrated device.

[0011] According to the preceding conventional method, the exposed partof the diffusion barrier layer 16C of the plug 16 is contacted to thedielectric layer 18.

[0012] There are several problems generated by the contact between thediffusion layer 16C and the dielectric layer 18. One problem is that thediffusion barrier layer 16C is oxidized during the process for formingthe dielectric layer 18, because the dielectric layer 18, such as theBST layer, is formed under oxygen gas atmosphere and at hightemperature. The oxidized part of the diffusion barrier layer 16C,exhibiting low dielectric constant, plays a role of a dielectric layerof a capacitor, thereby the capacitance of the capacitor is reduced. Theother problem is that the work function difference, between thediffusion barrier 16C and the dielectric layer 18, is low, thereby theleakage current is increased because of the low Schottky barrier height.

SUMMARY OF THE INVENTION

[0013] It is, therefore, an object of the present invention to provide asemiconductor memory device and a fabrication method capable ofpreventing the contact between a dielectric layer of a capacitor and adiffusion barrier of a plug.

[0014] It is, therefore, another object of the present invention toprovide a semiconductor memory device and a fabrication method capableof preventing the lowering the capacitance of a capacitor and theincreasing the leakage current between the lower electrode of acapacitor and a diffusion barrier of a plug.

[0015] In accordance with an aspect of the present invention, there isprovided a semiconductor memory device, comprising: a semiconductorsubstrate, wherein a gate electrode is formed on the semiconductorsubstrate, and wherein source/drain junctions are formed in thesemiconductor substrate; an interlayer insulating layer formed over thesemiconductor substrate; a plug formed in the interlayer insulatinglayer, wherein the plug comprises a diffusion barrier layer and aconducting layer, and wherein the conducing layer is formed with amaterial capable of flowing current nevertheless the conducting layer isoxidized; a lower electrode of capacitor contacted to the conducinglayer; a dielectric layer formed on the lower electrode; and an upperelectrode formed on the dielectric layer.

[0016] In accordance with another aspect of the present invention, thereis provided a method for fabricating semiconductor memory device,comprising the steps of: providing a semiconductor substrate, wherein agate electrode is formed on the semiconductor substrate, and whereinsource/drain junctions are formed in the semiconductor substrate;forming an interlayer insulating layer over the semiconductor substrate;etching the interlayer insulating layer to form a contact hole; forminga diffusion barrier layer and a conducting layer in the contact hole toform a plug, wherein the conducing layer is formed with a materialcapable of flowing current nevertheless the conducting layer isoxidized; forming a lower electrode contacted to the conducting layer;forming a dielectric layer on the lower electrode; and forming an upperelectrode on the dielectric layer.

[0017] In accordance with still further another aspect of the presentinvention, there is a method for fabricating semiconductor memorydevice, comprising the steps of: providing a semiconductor substrate,wherein a gate electrode is formed on the semiconductor substrate, andwherein source/drain junctions are formed in the semiconductorsubstrate; forming an interlayer insulating layer over the semiconductorsubstrate; etching the interlayer insulating layer to form a contacthole; forming a plug, wherein a diffusion barrier and a conducting layerin the contact hole to form the plug, and wherein the conducing layer isformed with a material capable of flowing current nevertheless theconducting layer is oxidized; forming a seed layer on the conductinglayer; forming a glue layer on the seed layer; forming a sacrificiallayer on glue layer; etching the sacrificial layer and the glue layer toform a opening defining a region of a lower electrode; forming a lowerelectrode on the seed layer in the opening; removing the sacrificiallayer and the seed layer; forming a dielectric layer on the lowerelectrode; and forming a upper electrode on the dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects and features of the present inventionwill become apparent from the following description of the preferredembodiments given in conjunction with the accompanying drawings, inwhich:

[0019]FIG. 1A to FIG. 1C are cross sectional views showing a method forfabricating a semiconductor memory device according to the conventionalmethod.

[0020]FIG. 2A to FIG. 2I are cross sectional views showing a method forfabricating a capacitor of a semiconductor device according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, a semiconductor memory device fabrication methodaccording to embodiments of the present invention will be described indetail referring to the accompanying drawings.

[0022] As shown in FIG. 2A, an interlayer insulating layer, composed ofa first insulating layer 21 and a second insulting layer 22, is formedover a semiconductor substrate 20, on which a determined lower structure(not shown), comprising an isolation layer, such as a field oxide layer,and a transistor including a gate insulating layer, a gate electrode andthe source/drain junctions. The second insulating layer 22 is formedwith a material of which etching selectivity is higher than the firstinsulating layer 21. In a preferred embodiment of the present invention,the first insulating layer 21 is formed by depositing a silicon oxidelayer to a thickness of 3000-8000 Å, and the second insulating layer 22is formed by depositing a silicon nitride layer to a thickness of 300 to1000 Å.

[0023] As shown in FIG. 2B, the second insulating layer 22 and the firstinsulating layer 21 are etched to form a contact hole 100 exposing oneof the source/drain junction (not shown) formed in the semiconductorsubstrate 20. And then, a polysilicon layer 23A, for forming a plug isdeposited to a thickness of 500-3000 Å on the second insulating layer 22and the on semiconductor substrate 20 in the contact hole. Thereafter,an etching process is performed to expose the surface of the secondinsulting layer 22 and to remove a part of the polysilicon layer 23A inthe contact hole. Thereby, the height difference 200 between the surfaceof the second insulating layer 22 and the surface of the polysiliconlayer 23A becomes 500 to 1500 Å.

[0024] As sown in FIG. 2C, an ohmic contact layer 23B and a diffusionbarrier layer 23C are formed, one by one, on the polysilicon layer 23A.Subsequently, a chemical mechanical polishing (hereafter, abbreviatedCMP) process is performed until the surface of the second insulatinglayer 22 is exposed. In a preferred embodiment of the present invention,the ohmic contact layer 23B is formed with TiSi_(x) and the diffusionbarrier layer 23C is formed with TiN, TiSiN, TiAlN, TaSiN, TaAlN, IrO₂or RuO₂. For forming the TiSi_(x), a Ti layer is deposited, an annealingprocess is performed for reaction between Ti atom in the titanium layerand Si atom in the polysilicon layer 23A, and a wet etching process isperformed to remove the Ti layer remaining on the second insulatinglayer 22 and the TiSi_(x) layer.

[0025] As shown in FIG. 2D, a part of the diffusion barrier layer 23C isetched using an etchant, such as a mixed gas comprising Cl₂ and BC1 ₃,to which the diffusion barrier layer 23C has higher etching selectivitythan the second insulting layer 22.

[0026] As shown in FIG. 2E, a conducting layer 23D is deposited on thesecond insulating layer 22 and the diffusion barrier layer 23C, and ablanket etching process or a CMP process is performed until the secondinsulating layer 22 is exposed. Thereby, the plug 23 composed ofpolysilicon layer 23A, the ohmic contact layer 23B, the diffusionbarrier 23C and the conducting layer 23D a, is completely formed. Theconducting layer 23D is formed with a material which can flow currenteven if it is oxidized. In the preferred embodiment of the presentinvention, Ru, Pt or Ir is deposited by using chemical vapor depositiontechnique, for forming the conducting layer 23D. On the other hand, theblanket etching process or the CMP process may be skipped, in order touse the conducting layer 34D as a seed layer for forming a lowerelectrode of a capacitor.

[0027] Also, the process for forming the polysilicon layer 23A may beomitted, in such case, the plug 23 is composed of the ohmic contactlayer 23B layer, the diffusion barrier layer 23C and the conductinglayer 24D. Moreover, the process for forming the ohmic contact layer 23Bcan be omitted, in such a case, the plug 23 is composed of thepolusilicon layer 23A, diffusion barrier layer 23C and the conductinglayer 24D. Accordingly, it is possible that the plug 23 is composed ofthe diffusion barrier layer 23C and the conducting layer 23D.

[0028] As shown in FIG. 2F, a seed layer 24 is formed on the conductinglayer 23D and the second insulating layer 22, thereafter a glue layer 25and a sacrificial layer 26 are stacked, one by one, on the seed layer24. In the preferred embodiment of the present invention, the seed layer24 is formed with Pt or Ru 50-100 Å thick, the glue layer 25 is formedwith TiN, TiAlN, TaN, TaSiN, Al₂O₃ or TiO₂ 50-500 Å thick, and thesacrificial layer 26 is formed with silicon oxide 5000-15000 Å thick. Incase that the conducting layer 23D is formed.

[0029] On the other hand, the processes for forming the seed layer 24and the glue layer 25 can be omitted depending the various methods forforming a lower electrode.

[0030] As shown in FIG. 2G, the sacrificial layer 26 and the glue layer25 is selectively etched to form opening 300 exposing the seed layer 24,and a lower electrode 27 is formed on the seed layer 24 in the opening300. In the preferred embodiment of the present invention, a Pt layer asthe lower electrode 27, is deposited to a thickness of 4000-12000 Å bythe electroplating. A current density of 0.1-20 mA/cm² is imposed onelectrodes for electroplating, with DC or DC pulse.

[0031] As shown FIG. 2H, the sacrificial layer 26, the glue layer 25 andthe seed layer 24 are removed to separate neighboring the lowerelectrodes 27. The sacrificial layer 26 and the glue layer 25 areremoved by a wet etching, and the seed layer 24 is removed by a dryetching. Also, the glue layer 25 can be removed by a dry etching.

[0032] According to the preceding process of the present invention, thediffusion barrier layer 23C of the plug 23 is not exposed, even if themask misalignment is occurred in the process for forming the opening300. That is, the conducting layer 23D, covering the diffusion layer23C, is exposed in case of occurring the mask misalignment.

[0033] As shown in FIG. 2I, a dielectric layer 28 is deposited on thelower electrode 27 and the second insulating layer 22. Thereafter, anupper electrode 29 is formed on the dielectric layer 28. In thepreferred embodiment of the present invention, a BST layer is depositedto a thickness of 150-500 Å at a temperature of 350-600° C. for formingthe dielectric layer 28, and an annealing for crystallizing thedielectric layer 28 is performed in an N₂ gas atmosphere at atemperature of 500-700° C. for 30-180 seconds, thereby dielectriccharacteristic of the dielectric layer 28 may be improved. The upperelectrode 29 is formed with a material, which can flow current even ifit is oxidized, such as Pt, Ru, Ir.

[0034] There are several advantages to form the conducing layer on thediffusion barrier. A first advantage is that it is possible to preventthe dielectric layer being contacted with the diffusion barrier. Asecond advantage is that it is possible to reduce the leakage current. Athird advantage is that it is possible to prevent the diffusion barrierfrom being exposed even if the mask misalign is occurred, thereby theannealing for crystallizing the dielectric layer can be performed at ahigh temperature. A fourth advantage is that it is possible to obtainhigh capacitance of the capacitor in the highly integrated semiconductordevice.

[0035] Although the preferred embodiments of the invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

What is claimed is:
 1. A semiconductor memory device, comprising: asemiconductor substrate, wherein a gate electrode is formed on thesemiconductor substrate, and wherein source/drain junctions are formedin the semiconductor substrate; an interlayer insulating layer formedover the semiconductor substrate; a plug formed in the interlayerinsulating layer, wherein the plug comprises a diffusion barrier layerand a conducting layer, and wherein the conducing layer is formed with amaterial capable of flowing current nevertheless the conducting layer isoxidized; a lower electrode of capacitor contacted to the conducinglayer; a dielectric layer formed on the lower electrode; and an upperelectrode formed on the dielectric layer.
 2. The semiconductor device asrecited in claim 1, the conducting layer is selected from a groupconsisting of Ru layer, Ir layer, Pt layer and Ir layer.
 3. Thesemiconductor device as recited in claim 1, the diffusion barrier layeris selected from a group consisting of TiN layer, TiSiN layer, TiAlNlayer, TaSiN layer, TaAlN layer, IrO₂ layer and RuO₂ layer.
 4. Thesemiconductor device as recited in claim 1, further comprising apolysilicon layer between the diffusion barrier layer and thesemiconductor substrate.
 5. The semiconductor device as recited in claim1, further comprising an ohmic contact layer between the diffusionbarrier layer and the semiconductor substrate.
 6. The semiconductordevice as recited in claim 5, further comprising a polysilicon layerbetween the ohmic contact layer and the semiconductor substrate.
 7. Amethod for fabricating semiconductor memory device, comprising the stepsof: providing a semiconductor substrate, wherein a gate electrode isformed on the semiconductor substrate, and wherein source/drainjunctions are formed in the semiconductor substrate; forming aninterlayer insulating layer over the semiconductor substrate; etchingthe interlayer insulating layer to form a contact hole; forming adiffusion barrier layer and a conducting layer in the contact hole toform a plug, wherein the conducing layer is formed with a materialcapable of flowing current nevertheless the conducting layer isoxidized; forming a lower electrode contacted to the conducting layer;forming a dielectric layer on the lower electrode; and forming an upperelectrode on the dielectric layer.
 8. The method as recited in claim 7,wherein the conducting layer is formed with Ir, Pt or Ru.
 9. The methodas recited in claim 8, the lower electrode is formed by anelectroplating by using the conducting layer as a see layer.
 10. Themethod as recited in claim 7, wherein the diffusion barrier layer isformed with TIN, TiSiN, TiAlN, TaSiN, TaAlN, IrO₂ or RuO₂.
 11. Themethod as recited in claim 7, wherein the dielectric layer is formedwith BaSrTiO₃ layer, and wherein the upper electrode is formed with Ptlayer, Ru layer or Ir layer.
 12. A method for fabricating semiconductormemory device, comprising the steps of: providing a semiconductorsubstrate, wherein a gate electrode is formed on the semiconductorsubstrate, and wherein source/drain junctions are formed in thesemiconductor substrate; forming an interlayer insulating layer over thesemiconductor substrate; etching the interlayer insulating layer to forma contact hole; forming a plug, wherein a diffusion barrier and aconducting layer in the contact hole to form the plug, and wherein theconducing layer is formed with a material capable of flowing currentnevertheless the conducting layer is oxidized; forming a seed layer onthe conducting layer; forming a glue layer on the seed layer; forming asacrificial layer on glue layer; etching the sacrificial layer and theglue layer to form a opening defining a region of a lower electrode;forming a lower electrode on the seed layer in the opening; removing thesacrificial layer and the seed layer; forming a dielectric layer on thelower electrode; and forming a upper electrode on the dielectric layer.13. The method as recited in claim 12, the step of forming the plugincluding: forming the diffusion barrier layer in the contact hole;etching the diffusion barrier to remove a part of the diffusion barrierlayer in the contact hole; and forming the conducting layer on thediffusion barrier layer.
 14. The method as recited in claim 12, whereinthe lower electrode is formed by an electroplating.
 15. The method asrecited in claim 13, wherein the conducting layer is formed with Ir, Ptor Ir, and wherein the diffusion barrier layer is formed with TiN,TiSiN, TiAlN, TaSiN, TaAlN, IrO₂ or RuO₂.
 16. The method as recited inclaim 15, wherein a silicon oxide layer and a nitride layer are stakedto form the interlayer insulating layer.
 17. The method as recited inclaim 16, wherein the diffusion barrier layer is etched with a mixed gascomprising C1 ₂ and BC1 ₃.
 18. The method as recited in claim 16, thedielectric layer is formed with a BaSrTiO₃ layer, and wherein the upperelectrode is formed with Pt layer, Ru layer or Ir layer.